The present application relates to semiconductor structures and methods of forming the same. More particularly, the present application relates to semiconductor structures that include a third type of metal gate stack that is located above an isolation structure and between a replacement metal gate n-type field effect transistor and a replacement metal gate p-type field effect transistor. The present application also relates to methods of forming such semiconductor structures utilizing a replacement gate, i.e., gate last, processing flow.
In the production of integrated circuits on semiconductor substrates, it is often necessary to selectively interconnect various doped zones or other different regions, connections or electrodes of the devices which are formed on the semiconductor substrate. For example, in field effect technology, it is often necessary to connect selectively gate electrodes to source/drain diffusions or to connect different gate electrodes together, or to connect different source/drain regions together. In forming the devices, it is necessary to provide interconnections which connect selectively only those regions which are desired to be interconnected and to prevent connections of those regions which must be electrically isolated, and which during processing require steps or techniques which assure that they will not be interconnected.
The interconnection between the various zones or regions is desirably done by a material which has a very high conductivity (i.e., a very low resistance). Thus, the interconnection should be done with materials that have very low resistivity so that minimal amounts of material can be used to provide the desired interconnection, and yet with these materials, the interconnections must be reliably made without shorting to undesired regions or without resulting opens or regions of high resistance within the interconnect lines or at the connections of the interconnect lines to the various regions.